蔡司首次登上 COMPUTEX 论坛，展示 AI 芯片到机架全链质量方案
Quality Innovation Powering AI: ZEISS Brings Quality to COMPUTEX Forum for the First Time
蔡司（ZEISS）今年首次把质量议题带上 COMPUTEX 2026 官方论坛舞台，强调质量正从制造支持职能转变为影响 AI 硬件性能、良率与交付能力的直接因素。蔡司工业质量解决方案电子客户细分全球负责人 Clive Yen 表示，算力需求激增让制造商面对创纪录订单，难点在于以一致质量实现规模化交付，公司正与 ODM 生态及 AI 服务器全价值链协作。蔡司研究显微镜解决方案全球销售负责人 Tonmoy Kundu 称，规模化下微小缺陷也可能成为主要瓶颈，制造商需要更快的洞察、更紧的工艺控制和可信的失效分析。论坛上蔡司将展示面向先进高带宽内存（HBM）的高分辨率无损检测与深度缺陷分析方案，以及面向共封装光学（CPO）的计量方案，用于保证 FAU 和 MPO 连接器在 51.2T+ 网络中的对准、耦合效率与长期传输可靠性。展馆方面，蔡司将展出覆盖晶圆工艺控制、先进封装、X 射线检测、电子显微镜、光学与数字显微镜及三坐标测量机的技术，应用聚焦芯片制造、PCB 可靠性、热管理系统、连接器质量和 L10-L11 机架机械件装配。COMPUTEX 2026 于 6 月 2-5 日在台北举行，蔡司将于 6 月 4 日 16:30-16:55 在 TaiNEX 2 701 室发表题为“Quality Innovation Across the AI Chip-to-Rack Stack”的演讲。
Taipei | 1 June 2026 | ZEISS Industrial Quality Solutions
ZEISS, a global leader in optics and optoelectronics, will bring the quality discussion to the official COMPUTEX 2026 Forum stage for the first time this year, highlighting the growing role of quality in scaling AI hardware.
As demand for AI infrastructure accelerates, quality is shifting from a manufacturing support function to a direct driver of performance, yield and delivery readiness. While public attention often centers on AI models, reliable hardware execution is becoming a decisive factor in AI deployment.
Behind every AI interaction are massive data centers powered by thousands of GPUs. As systems scale from chip to rack, defects in semiconductor packaging, printed circuit boards (PCB/A), cooling systems and high-speed interconnects can affect uptime, deployment speed and total cost.
"With compute demand surging, manufacturers face record orders, but the challenge is delivering at scale with consistent quality," said Clive Yen, Global Head of Electronics Customer Segment, ZEISS Industrial Quality Solutions. "As systems grow more complex, quality becomes critical to reliable deployment. This is why we work across the ODM ecosystem and the full AI server value chain to enable consistent, scalable quality."
"At scale, even small defects can become major bottlenecks," said Tonmoy Kundu, Global Head of Sales, ZEISS Research Microscopy Solutions. "Manufacturers need faster insight, tighter process control and trusted failure analysis to accelerate next-generation AI hardware."
ZEISS says it offers one of the industry’s most comprehensive quality portfolios across the AI hardware value chain, supporting customers from semiconductor packaging and PCB inspection to liquid cooling, optical connectivity and final rack integration.
At the forum, ZEISS will showcase solutions for advanced high-bandwidth memory (HBM), where rising stack heights and shrinking interconnect dimensions require high-resolution, non-destructive inspection and deep defect analysis.
The company will also present metrology solutions for co-packaged optics (CPO), where ultra-tight tolerances for FAU and MPO connectors are essential to maintain alignment, coupling efficiency and long-term transmission reliability in 51.2T+ networks.
At the exhibition hall, ZEISS will showcase technologies spanning wafer process control, advanced packaging, X-ray inspection, electron microscopy, light and digital microscopy, and coordinate measuring machines. Applications will focus on chip manufacturing, PCB reliability, thermal management systems, connector quality and L10-L11 rack mechanical parts assembly.
COMPUTEX 2026 runs June 2-5 in Taipei, where ZEISS will position quality as a foundational enabler of the next wave of AI growth. ZEISS will speak at the official COMPUTEX 2026 Forum on June 4, 4:30 p.m. to 4:55 p.m. at TaiNEX 2, Room 701, presenting "Quality Innovation Across the AI Chip-to-Rack Stack." The session will feature Tonmoy Kundu and Clive Yen.
来源：蔡司 · 工业计量新闻 · zeiss.com